Cpre 281 Homework Assignments

http://www.registrar.iastate.edu/students/exams/fallexamsThe final exam for CPRE 281 based on the first contact time is Thursday, Dec 15, 12.00noon – 2.00 pm. There will be NO makeup examsunless the reason falls in the university approved list (http://catalog.iastate.edu/academic_conduct/).Policy on CollaborationYou are encouraged to form study groups and discuss the reading materials assigned for this class. However, each student must write his/her own solutions/code/homework. Sharing of code is not allowed. No collaboration will be allowed during the exams. Students engaged in cheating practices will receive a failing grade in this course and will face further disciplinary action from the university. IMPORTANT: Cheating, plagiarism, and other academic misconducts will not be tolerated and will be handled according to the ISU's academic dishonesty procedures. http://catalog.iastate.edu/academic_conduct/#academicdishonestytextAttendanceYou are expected to attend ALLlectures. There is mandatory attendance for ALLlabs.If you have a valid reason to miss a class (e.g., because you are ill) then it is your responsibility to find out what we have talked about in class, including any announcements that were made during class from colleagues or friends. The instructor or teaching assistant will not repeat or duplicate lectures or lab instructions. You will have to request prior permission from the teaching assistant of your lab section for university excused absences when applicable. Appealing a GradeYou will have a one-weekwindow of appeal after each homework/lab/exam is graded and returned. The grade challenge must be in writing and must clearly state the specific problem on the homework/lab/exam in question and the reason for your challenge. The written statement and the original exam must be submitted to the instructor during the one-week window. After one week the grade cannot be changed.

Presentation on theme: "Instructor: Alexander Stoytchev CprE 281: Digital Logic."— Presentation transcript:

1 Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2 Algorithmic State Machine (ASM) Charts CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3 Administrative Stuff Homework 11 is due today Last homework for the semester!

4 Administrative Stuff Final Project (10% of your grade) Posted on the class web page (Labs section) This is due this week (during your lab)

5 Administrative Stuff The FINAL exam is scheduled for Wednesday Dec. 18 @ 7:30-9:30 AM That is 7:30 AM  It will be in this room.

6

7 Output signals or actions (Moore type) State name Condition expression 0 (False) 1 (True) Conditional outputs or actions (Mealy type) (a) State box(b) Decision box (c) Conditional output box Elements used in ASM charts [ Figure 6.81 from the textbook ]

8 Output signals or actions (Moore type) State name State Box [ Figure 6.81a from the textbook ]

9 Output signals or actions (Moore type) State name State Box Indicated with a rectangle Equivalent to a node in the State diagram The name of the state is written outside the box Moore-type outputs are written inside the box Only the output that must be set to 1 is written (by default, if an output is not listed it is set to 0)

10 Decision Box Condition expression 0 (False) 1 (True) [ Figure 6.81b from the textbook ]

11 Decision Box Indicated with a diamond shape Used for a condition expression that must be tested The exit path is chosen based on the outcome of the test The condition is on one or more inputs to the FSM Shortcut notation: w means “is w equal to 1?” Condition expression 0 (False) 1 (True)

12 Conditional Output Box Indicated with an oval shape Used for a Mealy-type output signals The outputs depend on the state variables and inputs The condition that determines when such outputs are generated is placed in a separate decision box [ Figure 6.81c from the textbook ] Conditional outputs or actions (Mealy type)

13 Some Examples

14 [ Figure 6.82 from the textbook ] Cz1=  Reset Bz0=  Az0=  w0= w1= w1= w0= w0= w1= [ Figure 6.3 from the textbook ] FSM ASM chart

15 [ Figure 6.83 from the textbook ] FSM ASM chart [ Figure 6.23 from the textbook ]

16 [ Figure 6.84 from the textbook ][ Figure 6.73 from the textbook ] FSM ASM chart

17 ASM Chart is different from a Flow Chart The ASM chart implicitly includes timing info It is assumed that the underlying FSM changes from one state to another on every active clock edge Flow charts don’t make that assumption.

18 Combinational circuit Y k Y 1 y k y 1 w 1 w n z 1 z m Outputs Next-state variables Present-state variables Inputs The general model for a sequential circuit [ Figure 6.85 from the textbook ]

19 The general model for a sequential circuit

20 Examples of Solved Problems

21 Example 6.12

22 Goal Design an FSM that detects if the previous two values of the input w were equal to 00 or 11 If either condition is true then the output z should be set to 1; otherwise to 0.

23 State Diagram [ Figure 6.86 from the textbook ]

24 State Table for the FSM [ Figure 6.87 from the textbook ] [ Figure 6.86 from the textbook ]

25 State Table for the FSM [ Figure 6.87 from the textbook ]

26 State-Assigned Table for the FSM [ Figure 6.88 from the textbook ]

27 State-Assigned Table for the FSM [ Figure 6.88 from the textbook ]

28 State-Assigned Table for the FSM

29

30 Next State and Output Expressions

31 An Improved State-Assigned Table [ Figure 6.89 from the textbook ][ Figure 6.87 from the textbook ] B,C, D, E – when y 3 =1

32 An Improved State-Assigned Table [ Figure 6.89 from the textbook ]

33 An Improved State-Assigned Table

34

35 Example 6.13

36 FSM that detects a sequence of two zeros [ Figure 6.90 from the textbook ]

37 Example 6.14

38 Goal Design an FSM that detects if the previous two values of the input w were equal to 00 or 11 If either condition is true then the output z should be set to 1; otherwise to 0. Implement this as a Mealy-type machine

39 [ Figure 6.91 from the textbook ] State Diagram

40 [ Figure 6.92 from the textbook ] Building the State Table

41 [ Figure 6.92 from the textbook ] State Table

42 [ Figure 6.93 from the textbook ] Building the State-Assigned Table

43 [ Figure 6.93 from the textbook ] State-Assigned Table

44 Example 6.15

45 Goal Implement this state-assigned Table using JK flip-flips

46 [ Figure 6.94 from the textbook ] Excitation table with JK flip-flops

47 JK Flip-Flops

48 Questions?

49 THE END

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